1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a device isolation structure of a MOS transistor.
2. Description of the Related Art
As is well known, in a conventional device isolation structure, a shallow trench with a depth of about 0.5 μm or less is formed in a silicon substrate, and silicon oxide is filled in the trench, thereby effecting insulation between transistors. This technique is generally called STI (Shallow Trench Isolation).
In particular, the filled silicon oxide has a lower linear expansion coefficient than silicon, and thus causes a compressive stress in the surrounding silicon. The reason for this is that if silicon oxide, which is deposited at high temperatures, is cooled down to room temperature, the silicon oxide does not easily contract while the surrounding silicon contracts due to heat.
The compressive stress that occurs at end portions of the trench gradually attenuates as the distance from the end portions becomes greater. However, in a case where the distance between the end portion of the trench and the gate is small, the compressive stress does not greatly attenuate and it acts in a silicon region under the gate. The compressive stress, in particular, decreases the carrier mobility in an n-MOS transistor, leading to an adverse effect on the device, such as a decrease in ON-current.
Jpn. Pat. Appln. KOKAI Publication No. 2003-179157 and Jpn. Pat. Appln. KOKAI Publication No. 2003-273206 disclose such techniques that a tensile stress is additionally provided by interposing a silicon nitride film between silicon oxide, which is buried in a trench, and a silicon oxide film on the inner wall of the trench, or a compressive stress due to the buried silicon oxide is canceled by the tensile stress of the silicon nitride film.